As is known in the art, dynamic random access memories (DRAMs) are used extensively in a wide range of applications. A DRAM typically includes an array of memory cells, each cell comprising an access transistor, typically a metal oxide semiconductor field effect transistor (MOSFET), coupled in series with a capacitor.
A portion 10 of an array is shown in FIG. 1, which illustrates two complementary pairs of bitlines BL and BL′. While this figure only illustrates eight memory cells, it is known to fabricate DRAMs with millions of cells. Each bitline pair BL and BL′ is coupled to equalization/precharge circuitry and a sense amplifier, collectively labeled 12. Although not illustrated, many bitline pairs (and respective circuitry 12) are typically provided.
Each memory cell includes an access transistor 14 coupled in series with a capacitor 16. As shown in the figure, one source/drain region of transistor 14 is coupled to the bitline BL (or BL′). The other source/drain region is coupled to one of the plates of respective capacitor 16. The other plate of capacitor 16 is coupled to a common plate reference voltage.
To select a particular memory cell, a select voltage is applied to one of the wordlines WL0-WL3. As illustrated in FIG. 1, the gate of each pass transistor 14 is coupled to one of the wordlines WL0-WL3. As shown, each wordline will extend across other bitlines and couple to the gates of pass transistors of memory cells coupled to those bitlines.
The bitline pair BL0 and BL0′ (or BL1 and BL1′) is selected by applying a select voltage to the select transistors 18. When the select transistors 18 are selected, the differential voltage signal across the bitline pair will be transferred to input/output lines I/O and I/O′. In this manner, the state stored in the one memory cell that is coupled to the selected wordline and selected bitline will be transferred to the input/output lines.
As shown in the simplified drawing of FIG. 1, the DRAM device includes transistors (e.g., 14) in the array and other transistors (e.g., 18) in the support circuitry. To interconnect these devices, various portions of each of these transistors will need to be connected, typically using metal wirings. The preferred embodiments of the present invention relate to methods of connecting to these portions of the transistor devices.